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List of Names
- Language type:
M - Mathematical or Simulation
VHDL is a modeling and simulation language
intended for study and design of digital
integrated circuits. The name is an
acronym for VHSIC Hardware Description
Language. The syntax and general
appearance of VHDL are similar to that of
Ada, but the semantic structure is quite
A VHDL model consists of a
hierarchy of entities, these entities
usually directly correspond to the parts of
the digital system under study.
Entities operate in parallel during
simulation; the simulations use a
kind of timed dataflow model that is adjustable
by the user (so as to accurately
represent a real circuit or chip).
operation of the various entities
can be very simple, like a small
expression, or very complex. VHDL
supports subroutines and functions as
well as conventional sequential
Data types in VHDL include bits,
integers, reals, time, arrays,
and records. The support for enumerated
types and their use is very good. (Because
most simulations of digital circuits model the
state of a digital signal with more than just
VHDL has good support for modularity and
for separation of
interface and implementation of entities.
First, it support generics for entities;
and second, the interface to an entity
is always separate from the description
of its operation.
This allows simulation's structure to be
built up once, but simulated for several
different hardware technologies.
A variety of VHDL implementations are
available from commercial CAD vendors.
At least one free implementation is
available for Unix systems as
part of the ALLIANCE
educational VLSI package.
M.R. Shahdad et al, 1985; IEEE Standard 1076, 1987.
- See Also:
VHDL is a remarkable complete procedural
block-structured language, considering
that it was not intended for application
VHDL was originally standardized in 1987 as
IEEE 1076, and revised six years later as
IEEE 1076-1993; there
is also an analog modeling extension which
is IEEE 1076.1. Unfortunately, there does
not seem to be a copy of the standard
available as HTML.
- Sample code:
-- Behavioral model of a D flip-flop, from
-- the US Army FCIM VHDL Tutorial.
ENTITY mydff IS
GENERIC(q_out, qb_out :time);
PORT(preset, clear, din, clock: :IN std_logic;
q, qb : :OUT std_logic);
ARCHITECTURE behavioral OF mydff IS
mydff_proc : PROCESS(preset, clear, clock)
VARIABLE int_q :std_logic;
IF preset = '0' AND clear = '0' THEN
IF(clock'EVENT) AND (clock = '1') THEN
int_q := din;
ELSEIF preset = '1' AND clear ='0' THEN
int_q := '1';
ELSEIF clear = '1' AND preset = '0' THEN
int_q := '0';
int_q := 'X';
q <= int_q AFTER q_out;
int_q := NOT(int_q);
qb <= int_q AFTER qb_out;
END PROCESS mydff_proc;
Descriptions in this dictionary are ©1997-99 Neal Ziring. Some
examples copyright of their respective authors. Some
technologies and languages are trademarked. Permission to
copy descriptions is granted as long as authorship credit is preserved.
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Dictionary and script maintained by Neal Ziring, last major modifications 3/18/98. Most recent
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